Multi-time programmable (MTP) memories have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security ID, and many other applications. Incorporating MTP memories nonetheless also typically comes at the expense of some additional processing steps. Some of the existing approaches to constructing MTP memories tend to suffer from slow access time, smaller coupling ratio and/or large cell size. Some of the existing approaches utilize band-to-band tunneling hot hole (BBHH) for erasing operation, but requires high junction band voltage and more process steps. Other existing approaches need additional coupling erase gate and coupling capacitor, and hence require more area.
Therefore, there is a need for a simple and cost-free MTP structure to create non-volatile memory cells with the standard complementary metal-oxide-semiconductor (CMOS) platform.